“AUXCELL_GEN” tool is developed to create a technology agnostic circuit design platform automating the process of Pareto optimization to meet the user constraints for each of the auxiliary cells and generate the required output views such as the CDL netlist, .lib files, GDS in STD cell format and LEF file. The output of this task will be a library of auxiliary cells used in the synthesis and APR of the analog blocks.
IDEA & POSH Integration Exercises – January 2019 Demos
Video 1 demonstrates the generation of the Tri-state buffer Auxcell required for the DLDO generator by exploring the Pareto design space satisfying the minimum power delay product in TSMC 65nm PDK. It also shows the generation of the CDL netlist and .lib files for three corners (TT, FF, and SS) that will be used in the synthesis and PNR of the DLDO at the top-level integration.
Video 1: AUXCELL_GEN tool