We designed a fully-synthesized ADPLL for BLE transmitter using standard digital tools. To overcome the PnR induced non-linearity and resolution limit of embedded TDC (EMBTDC), we used Vernier delay-line TDC (DLTDC) as fine TDC to further quantize the remaining time error after EMBTDC quantization. The DLTDC is also used to measure and record the quantization levels of EMBTDC and the resulting LUT is used in the decoding to compensate the delay mismatches in DCO (non-linearity of EMBTDC). The Design can be re-generated or modified by other users from https://github.com/idea-fasoc/fasoc/tree/master/generators/pll-gen. The README of this page provides the instructions about building the block. The design parameters of DCO and DLTDC are shown below.
DTC-unit design parameters
DLTDC design parameters – Each DTC unit name is a pre-fix for its DTC parameters. (Ex: pre_ls_ref_ncc_tune refers to ncc_tune of pre_ls_ref)
DCO design parameters