All-Digital PLL, a synthesizable clock generation circuit, is implemented based on digital standard cells and auxiliary cells. Embedded TDC is used for phase comparison, which avoids the needs of DCO period normalization. The fractional phase error generated from the TDC gets combined with the integer error, providing a complete phase error information for digital loop filter, which will modify the frequency control word of DCO accordingly. The digital domain operates with retimed reference clock to avoid any metastability issue. The performance of synthesizable ADPLL has been proven by numerous publications.

ADPLL diagram

Figure 1: ADPLL Block Diagram

Adopting a full digital flow that includes automatic place and route (APR), the whole design procedure can be automated using the auxiliary cells “Fully differential Tri-State Buffer” and “Differential Switched Capacitor“. The goal of this task is to thus generate a tool that automatically designs ADPLLs of various frequencies and performances according to user demand. Below are the targeted user spec ranges, which will be updated in the future with more specs added for TSMC 65nm and TSMC 40nm technology node:

DLDO Generator Input Spec Ranges

Frequency Range100MHz – 4GHz
Frequency Resolution Range13KHz – 4.5MHz

IDEA & POSH Integration Exercises – January 2019 Demos

Demo 1: DCO Model Generation
Video 1 shows the automatic model generation procedure for DCO. It can be summarized as:
a.) Automatically generating 63 netlists, 63 testbenches which has 15 parametric sweeps,
b.) Running Hspice simulation,
c.) Reading the simulation results and calculate model constants, which characterizes DCO specs (frequency range, frequency resolution, phase noise, power) for specific aux-cell and PDK.
d.) Calculation of the maximum error percentage of the generated model by comparing with the simulation results.

Video 1: DCO_MODEL tool 

Demo 2. Spec to design conversion of DCO
Video 2 shows the tool searching design solution for given user specifications. It uses the mathematical model generated in Demo 1 to sequentially narrow down the design space by calculating possible solutions for each specification. The video shows the result design parameters for 3 sets of input specs. The tool also produces the predicted specs of generated design, which mostly has margins compared to given user specs. 

Video 2: DCO_GEN tool