Journal Publications
Y. K. Cherivirala and D. D. Wentzloff, “A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 5, pp. 1769-1773, May 2023, doi: 10.1109/TCSII.2023.3257686.
K. Kwon, O. A. B. Abdelatty and D. D. Wentzloff, “PLL Fractional Spur’s Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter,” in IEEE Journal of Solid-State Circuits, vol. 58, no. 5, pp. 1271-1284, May 2023, doi: 10.1109/JSSC.2023.3236640.
Y. Park, D. D. Wentzloff, “A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 58, No. 7, July 2011, pp. 1511-1517.
Y. Park, D. D. Wentzloff, “An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell Library,”IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 5, May 2011, pp. 1147-1157.
Conference Proceedings
K. Kwon and D. D. Wentzloff, “Synthesizable ADPLL Generator: From Specification to GDS,” 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Funchal, Portugal, 2023, pp. 1-4, doi: 10.1109/SMACD58065.2023.10192175.
Y. K. Cherivirala, M. Saligane and D. D. Wentzloff, “An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation,” 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181884.
S. Kamineni, A. Sharma, R. Harjani, S. S. Sapatnekar and B. H. Calhoun, “AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells,” 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6, doi: 10.23919/DATE56975.2023.10137270.
K. Kwon, O. Abdelatty and D. Wentzloff, “Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology,” 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, USA, 2022, pp. 155-158, doi: 10.1109/RFIC54546.2022.9863190.
S. Kamineni, S. Gupta, and B. H. Calhoun, “MemGen: An open-source frame-work for autonomous generation of memory macros,” in IEEE Custom Integrated Circuits Conference (CICC), IEEE, 2021.
Li Xu, Jeongsup Lee, Mehdi Saligane, David Blaauw and Dennis Sylvester, “Design Techniques of Integrated Power Management Circuits for Low Power Edge Devices,” in IEEE Custom Integrated Circuits Conference (CICC), April 2021 (invited).
T. Ajayi, S. Kamineni, Y. K. Cherivirala, M. Fayazi, K. Kwon, M. Saligane, S. Gupta, C. Chen, D. Sylvester, D., R. Dreslinski Jr, B. Calhoun, D. Wentzloff, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation,” 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SoC), Salt Lake City, USA, 2020 (Best Paper Nominee).
D. M. Moore, J. A. Fredenburg, M. Faisal, D. D. Wentzloff, “Static Timing Analysis for Ring Oscillators,” Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018.
M. Faisal, N. E. Roberts, D. D. Wentzloff, “A 300nW near-threshold 187.5–500 kHz programmable clock generator for ultra low power SoCs,” in SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, Oct. 2015, pp.1-3, 5-8.
E. Ansari, D. D. Wentzloff, “A 5mW 250MS/s 12-bit Synthesized Digital to Analog Converter,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2014, pp. 1-4.
M. Faisal, D. D. Wentzloff, “An Automatically Placed-and-Routed ADPLL for the MedRadio Band using PWM to Enhance DCO Resolution,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013, pp. 115-118.
Y. Park, D. D. Wentzloff, “An All-Digital PLL Synthesized from a Digital Standard Cell Library in 65nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011, pp 1-4.
M. Faisal, Y. Park, D. D. Wentzloff, “Reconfigurable Firmware-Defined Radios Synthesized from Standard Digital Logic Cells,” SPIE Defense, Security, and Sensing Conference, Apr. 2011.
Y. Park, D. D. Wentzloff, “An All-Digital 12pJ/pulse 3.1-6.0GHz IR-UWB Transmitter in 65nm CMOS,” IEEE International Conference on Ultra-Wideband, Sep. 2010.
Y. Park, D. D. Wentzloff, “A Cyclic Vernier Time-to-Digital Converter Synthesized from a 65nm CMOS Standard Library,” IEEE International Symposium on Circuits and Systems (ISCAS), June 2010, pp. 3561-3564.
Y. Park, D. D. Wentzloff, “IR-UWB Transmitters Synthesized from Standard Digital Library Components,” IEEE International Symposium on Circuits and Systems (ISCAS), June 2010, pp. 3296-3299.
Y. Park, D.D. Wentzloff, “All-digital synthesizable UWB transmitter architectures,” IEEE International Conference on Ultra-Wideband(ICUWB), Sep. 2008, pp.29-32.
Posters
T. Ajayi, Y. K. Cherivirala, K. Kwon, S. Kamineni, M. Saligane, M. Fayazi, S. Gupta, C.-H. Chen, D. Sylvester, D. Blaauw, R. Dreslinski Jr, B. Calhoun, D. D. Wentzloff, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform,” 2020 IEEE Hot Chips 32 Symposium (HCS), August 2020.
Articles
T. Ansell and M. Saligane, “The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : Invited Paper,” 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-8.